Tentative support for avx512f extensions to 256 bit registers#1345
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serge-sans-paille wants to merge 1 commit into
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Tentative support for avx512f extensions to 256 bit registers#1345serge-sans-paille wants to merge 1 commit into
serge-sans-paille wants to merge 1 commit into
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In addition to missing instructions (e.g. bas on int64_t etc) this mostly changes the mask representation from vector register to scalar, thus the big diff.
Contributor
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Are we sure that we only need avx512f for this? It seems to me that instructions like https://diamondinoia.com/simdref/#_mm256_cmp_epi32_mask requires avx512f + VL. Let me know where I am wrong. Cheers, |
Contributor
Author
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You're right, all of this requires avx512f+avx512vl. It turns out most build have both (see https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512) but we currently don't have anything to model avx512vl, which should be the parent of avx512f_256. |
Contributor
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I guess it might be called avx512vl_256 at that point as we will also have avx512vl_128. What do you think? I agree, most CPU have 512+extensions. |
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In addition to missing instructions (e.g. bas on int64_t etc) this mostly changes the mask representation from vector register to scalar, thus the big diff.